Presentation 2006-08-17
An on-chip sampling oscilloscope based on ramp waveform division scheme
Kenichi INAGAKI, Danardono Dwi ANTONO, Makoto TAKAMIYA, Shigetaka KUMASHIRO, Takayasu SAKURAI,
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Abstract(in English) An on-chip sampling oscilloscope with 1ps timing resolution is realized in 90nm CMOS process based on a proposed ramp wave form division scheme for precise signal integrity and power-line integrity measurement. The resolution in time is variable from 1ps to 64ps in 64 steps. A novel on-chip inductance measurement procedure is also proposed.
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Keyword(in English) sampling oscilloscope / signal integrity
Paper # SDM2006-129,ICD2006-83
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Conference Date 2006/8/10(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An on-chip sampling oscilloscope based on ramp waveform division scheme
Sub Title (in English)
Keyword(1) sampling oscilloscope
Keyword(2) signal integrity
1st Author's Name Kenichi INAGAKI
1st Author's Affiliation Center for Collaborative Research, The University of Tokyo()
2nd Author's Name Danardono Dwi ANTONO
2nd Author's Affiliation Sony Corporation
3rd Author's Name Makoto TAKAMIYA
3rd Author's Affiliation Center for Collaborative Research, The University of Tokyo
4th Author's Name Shigetaka KUMASHIRO
4th Author's Affiliation NEC Electronics Corporation
5th Author's Name Takayasu SAKURAI
5th Author's Affiliation Center for Collaborative Research, The University of Tokyo
Date 2006-08-17
Paper # SDM2006-129,ICD2006-83
Volume (vol) vol.106
Number (no) 207
Page pp.pp.-
#Pages 6
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