Presentation 2006-09-25
Analysis of the Scaling Feasibility in SRAM by Mixed-mode 3-dimentional Device Simulation
Ryo Tanabe, Yoshio Ashizawa, Hideki Oka,
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Abstract(in English) In the progress of CMOS circuits' miniaturization, SRAM is considered to set a limit to the progress. In this paper, problems of SRAM development are picked up and their solutions are investigated by 3D Mixed-mode TCAD simulation We pick up the fluctuations of structure, discrete dopant and circuit delay. In addition, we will show the relationship between SRAM characteristics (Static Noise Margin and I_ and I_) and some physical effects (Quantum effect and Gate direct tunneling).
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SRAM / FinFET / Mixed-mode / TCAD / MOS / Quantum Effect / Tunneling Current / Scaling / Random Dopant Fluctuation
Paper # VLD2006-36,SDM2006-157
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Committee SDM
Conference Date 2006/9/18(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis of the Scaling Feasibility in SRAM by Mixed-mode 3-dimentional Device Simulation
Sub Title (in English)
Keyword(1) SRAM
Keyword(2) FinFET
Keyword(3) Mixed-mode
Keyword(4) TCAD
Keyword(5) MOS
Keyword(6) Quantum Effect
Keyword(7) Tunneling Current
Keyword(8) Scaling
Keyword(9) Random Dopant Fluctuation
1st Author's Name Ryo Tanabe
1st Author's Affiliation Fujitsu Laboratories Ltd.()
2nd Author's Name Yoshio Ashizawa
2nd Author's Affiliation Fujitsu Laboratories Ltd.
3rd Author's Name Hideki Oka
3rd Author's Affiliation Fujitsu Laboratories Ltd.
Date 2006-09-25
Paper # VLD2006-36,SDM2006-157
Volume (vol) vol.106
Number (no) 256
Page pp.pp.-
#Pages 6
Date of Issue