Presentation | 2006-09-25 Peak Power Reduction in LSI by Clock Scheduling Yosuke TAKAHASHI, Atsushi TAKAHASHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The reduction of peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise, and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of combinational logic elements. In this paper, we propose a fast power estimation method that considers switching probability of combinational logic elements and a clock scheduling approach to reduce the peak power. The validity of proposed method is shown by HSPICE simulation in which complete synchronous circuits and circuits with clock schedule obtained by the proposed method are compared. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | clock-scheduling / general-synchronous circuit / peak power / power estimation |
Paper # | VLD2006-35,SDM2006-156 |
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Committee | SDM |
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Conference Date | 2006/9/18(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Peak Power Reduction in LSI by Clock Scheduling |
Sub Title (in English) | |
Keyword(1) | clock-scheduling |
Keyword(2) | general-synchronous circuit |
Keyword(3) | peak power |
Keyword(4) | power estimation |
1st Author's Name | Yosuke TAKAHASHI |
1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
2nd Author's Name | Atsushi TAKAHASHI |
2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
Date | 2006-09-25 |
Paper # | VLD2006-35,SDM2006-156 |
Volume (vol) | vol.106 |
Number (no) | 256 |
Page | pp.pp.- |
#Pages | 6 |
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