Presentation 2006-09-13
Verification of MRSL based S-BOX in AES as a countermeasure against DPA
Minoru SASAKI, Keisuke IWAI, Takakazu KUROKAWA,
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Abstract(in English) The composing method of S-BOX in AES using composite fields is effective to implement compact cryptosystem, since the circuit scale can be greatly reduced. Recently, since it has become important for cryptosystem to apply tamper resistance, several methods to consist inversion operation circuit with random masked logic at module level have been proposed for DPA countermeasures. On the other hand, RSL (Random Switching Logic) gate that masks internal variables with random value at the primitive gate level had been also proposed. In this research, we propose MRSL (Modified RSL) to improve RSL. Moreover, implementation of a S-BOX circuit composed with MRSL on FPGA (Virtex1000), and its evaluation of DPA countermeasure ability is also shown.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Side Channel Attack / DPA / Countermeasure / AES / FPGA
Paper # ISEC2006-77
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Committee ISEC
Conference Date 2006/9/6(1days)
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Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Verification of MRSL based S-BOX in AES as a countermeasure against DPA
Sub Title (in English)
Keyword(1) Side Channel Attack
Keyword(2) DPA
Keyword(3) Countermeasure
Keyword(4) AES
Keyword(5) FPGA
1st Author's Name Minoru SASAKI
1st Author's Affiliation Department of Computer Science, National Defense Academy()
2nd Author's Name Keisuke IWAI
2nd Author's Affiliation Department of Computer Science, National Defense Academy
3rd Author's Name Takakazu KUROKAWA
3rd Author's Affiliation Department of Computer Science, National Defense Academy
Date 2006-09-13
Paper # ISEC2006-77
Volume (vol) vol.106
Number (no) 235
Page pp.pp.-
#Pages 8
Date of Issue