| Presentation | 2006-09-26 A Novel Asymmetric Raised Source/Drain Extension Structure for 32nm-node MOSFETs : An Ultimate Planar MOSFET Tsutomu IMOTO, Yasushi TATESHITA, Toshio KOBAYASHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel asymmetric MOSFET structure is proposed which provides an excellent tradeoff between current drivability and manufacturability for planar MOSFET technology. To achieve this, the "corner effect" is utilized to suppress short channel effects, while degradation in current drivability caused by the corner effect is avoided by an asymmetric design. Using simulation, it is shown that this structure enlarges the tolerance for the junction depth of source/drain extensions by a factor of three, without sacrificing current drivability, compared to the optimal symmetric structure also found in this work. This asymmetric structure is a superior design strategy for planar MOSFETs and can be considered as one of the most promising candidates for 32nm-node MOSFETs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asymmetric structure / corner effect / short channel effects / current drivability / process margin |
| Paper # | VLD2006-45,SDM2006-166 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2006/9/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Novel Asymmetric Raised Source/Drain Extension Structure for 32nm-node MOSFETs : An Ultimate Planar MOSFET |
| Sub Title (in English) | |
| Keyword(1) | asymmetric structure |
| Keyword(2) | corner effect |
| Keyword(3) | short channel effects |
| Keyword(4) | current drivability |
| Keyword(5) | process margin |
| 1st Author's Name | Tsutomu IMOTO |
| 1st Author's Affiliation | Semiconductor Technology Development Goup, Semiconductor Business Unit, SONY Corp.() |
| 2nd Author's Name | Yasushi TATESHITA |
| 2nd Author's Affiliation | Semiconductor Technology Development Goup, Semiconductor Business Unit, SONY Corp. |
| 3rd Author's Name | Toshio KOBAYASHI |
| 3rd Author's Affiliation | Semiconductor Technology Development Goup, Semiconductor Business Unit, SONY Corp. |
| Date | 2006-09-26 |
| Paper # | VLD2006-45,SDM2006-166 |
| Volume (vol) | vol.106 |
| Number (no) | 255 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |