Presentation | 2006-09-26 Analysis of Underlapped Single-Gate Ultrathin SOI MOSFET with High-k Gate Dielectric : characteristic advancement and suppression of dispersion Yoshimasa YOSHIOKA, Yasuhisa OMURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this technical report, we present performance prospect of underlapped single-gate ultrathin (USU) SOI MOSFET with a high-κ gate dielectric regarding suppression of GIDL current and advancement of switching speed. In addition, USU SOI MOSFET has some advantages such as suppression of device characteristics dispersion as well as suppression of short-channel effects. We also address the design guideline of USU SOI MOSFET in order to gain both better d.c. and a.c. performance. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | ultrathin SOI / intrinsic delay time / underlap structure / GIDL current / high-k gate dielectric |
Paper # | VLD2006-44,SDM2006-165 |
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Committee | VLD |
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Conference Date | 2006/9/19(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Analysis of Underlapped Single-Gate Ultrathin SOI MOSFET with High-k Gate Dielectric : characteristic advancement and suppression of dispersion |
Sub Title (in English) | |
Keyword(1) | ultrathin SOI |
Keyword(2) | intrinsic delay time |
Keyword(3) | underlap structure |
Keyword(4) | GIDL current |
Keyword(5) | high-k gate dielectric |
1st Author's Name | Yoshimasa YOSHIOKA |
1st Author's Affiliation | Graduate School of Engineering, Kansai University() |
2nd Author's Name | Yasuhisa OMURA |
2nd Author's Affiliation | ORDIST, Kansai University |
Date | 2006-09-26 |
Paper # | VLD2006-44,SDM2006-165 |
Volume (vol) | vol.106 |
Number (no) | 255 |
Page | pp.pp.- |
#Pages | 6 |
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