Presentation	2006-09-26 A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory Akihiko TSUKAHARA, Akinori KANASUGI,
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Abstract(in English)	This paper proposes a novel processor for genetic algorithm (GA) using dynamically reconfigurable memory. In general GA, the number of population is always constant. However, the accuracy of the solution is low in the first-half stage. Then, the number of population is doubled at the expense of the accuracy of the solution, and the searching ability is improved in the first-half stage. Moreover, the number of population is reduced by half, and accuracy is improved in the second-half stage. As a result, the searching ability is improved without increasing the memory capacity. The processor was designed by using VHDL and the circuit was simulated. The effectiveness of the proposal processor was confirmed by logic simulations.
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Keyword(in English)	Genetic Algorithm / Dynamically Reconstruction / FPGA
Paper #	VLD2006-39,SDM2006-160
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Conference Information
Committee	VLD
Conference Date	2006/9/19(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory
Sub Title (in English)
Keyword(1)	Genetic Algorithm
Keyword(2)	Dynamically Reconstruction
Keyword(3)	FPGA
1st Author's Name	Akihiko TSUKAHARA
1st Author's Affiliation	Tokyo Denki University()
2nd Author's Name	Akinori KANASUGI
2nd Author's Affiliation	Tokyo Denki University
Date	2006-09-26
Paper #	VLD2006-39,SDM2006-160
Volume (vol)	vol.106
Number (no)	255
Page	pp.pp.-
#Pages	6
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