| Presentation | 2006-09-01 Equivalent circuit reduction of CMOS output buffer for high speed simulation of power supply noise Junya YAMAMOTO, Osami WADA, Takashi HISAKADO, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To realize high-speed noise simulation at board level, an output buffer model of a CMOS inverter circuit is simplified as an example for power-supply noise simulation by SPICE. When inverters are switching simultaneously, the power-supply noise is reproduced in good accuracy with an equivalent single inverter composed of a PMOS and an NMOS; each of them represents a group of FETs connected in parallel respectively, and the model parameters of each MOSFET are determined based on the physical dimensions of each transistor. When inverters are edge-controlled and operating in different timing, the power-supply noise can also be reproduced with an equivalent single inverter and input resistors that reflect the delay time of the input signals of the original circuit. The values of resistances are calculated based on the delay times of input signals. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | EMC / power supply noise / SPICE simulation / CMOS / edge-controlled / device model |
| Paper # | EMCJ2006-46 |
| Date of Issue |
| Conference Information | |
| Committee | EMCJ |
|---|---|
| Conference Date | 2006/8/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electromagnetic Compatibility (EMCJ) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Equivalent circuit reduction of CMOS output buffer for high speed simulation of power supply noise |
| Sub Title (in English) | |
| Keyword(1) | EMC |
| Keyword(2) | power supply noise |
| Keyword(3) | SPICE simulation |
| Keyword(4) | CMOS |
| Keyword(5) | edge-controlled |
| Keyword(6) | device model |
| 1st Author's Name | Junya YAMAMOTO |
| 1st Author's Affiliation | Department of Electrical Engineering Kyoto University() |
| 2nd Author's Name | Osami WADA |
| 2nd Author's Affiliation | Department of Electrical Engineering Kyoto University |
| 3rd Author's Name | Takashi HISAKADO |
| 3rd Author's Affiliation | Department of Electrical Engineering Kyoto University |
| Date | 2006-09-01 |
| Paper # | EMCJ2006-46 |
| Volume (vol) | vol.106 |
| Number (no) | 224 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |