| Presentation | 2006-09-15 A Parametric Study of Packet-Switched FPGA Overlay Networks Daihan WANG, Hiroki MATSUTANI, Masato YOSHIMI, Michihiro KOIBUCHI, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The constantly upgrading gate capacity of FPGAs enables us to implement a complex system on a chip. A packet-switched network presents to share network resources by multiple connections, so as to make the best use of link bandwidth. This study investigates the suitable overlay interconnects on FPGAs in terms of the amount of hardware, and throughput based on a parametric approach. Because the number of ports on a router sometimes dominates the amount of hardware for router, and its throughput performance, it has been chosen as a parameter. Based on a typical implementation of NoC router, various networks have been generalized and evaluated, in the case of both 16 hosts and 36 hosts. Evaluation results show that for small systems with 16 hosts or less, a full-crossbar switch is advantageous from the viewpoint of both throughput performance and hardware cost. On the other hand, when systems become large, the partitioned networks are efficient from the viewpoint of hardware cost. When the performance requirement is not so critical, we should select partitioned topology which requires minimum hardware and use some localization methods to improve the performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Networks-on-chip / Router / Node degree / Simulation |
| Paper # | RECONF2006-32 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/9/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Parametric Study of Packet-Switched FPGA Overlay Networks |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Networks-on-chip |
| Keyword(3) | Router |
| Keyword(4) | Node degree |
| Keyword(5) | Simulation |
| 1st Author's Name | Daihan WANG |
| 1st Author's Affiliation | Department of Information and Computer Science, Keio University() |
| 2nd Author's Name | Hiroki MATSUTANI |
| 2nd Author's Affiliation | Department of Information and Computer Science, Keio University |
| 3rd Author's Name | Masato YOSHIMI |
| 3rd Author's Affiliation | Department of Information and Computer Science, Keio University |
| 4th Author's Name | Michihiro KOIBUCHI |
| 4th Author's Affiliation | National Institute of Informatics |
| 5th Author's Name | Hideharu AMANO |
| 5th Author's Affiliation | Department of Information and Computer Science, Keio University |
| Date | 2006-09-15 |
| Paper # | RECONF2006-32 |
| Volume (vol) | vol.106 |
| Number (no) | 247 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |