| 講演名 | 2006-09-15 A Parametric Study of Packet-Switched FPGA Overlay Networks , |
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| PDFダウンロードページ |  PDFダウンロードページへ |
| 抄録(和) | |
| 抄録(英) | The constantly upgrading gate capacity of FPGAs enables us to implement a complex system on a chip. A packet-switched network presents to share network resources by multiple connections, so as to make the best use of link bandwidth. This study investigates the suitable overlay interconnects on FPGAs in terms of the amount of hardware, and throughput based on a parametric approach. Because the number of ports on a router sometimes dominates the amount of hardware for router, and its throughput performance, it has been chosen as a parameter. Based on a typical implementation of NoC router, various networks have been generalized and evaluated, in the case of both 16 hosts and 36 hosts. Evaluation results show that for small systems with 16 hosts or less, a full-crossbar switch is advantageous from the viewpoint of both throughput performance and hardware cost. On the other hand, when systems become large, the partitioned networks are efficient from the viewpoint of hardware cost. When the performance requirement is not so critical, we should select partitioned topology which requires minimum hardware and use some localization methods to improve the performance. |
| キーワード(和) | |
| キーワード(英) | FPGA / Networks-on-chip / Router / Node degree / Simulation |
| 資料番号 | RECONF2006-32 |
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| 研究会情報 | |
| 研究会 | RECONF |
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| 開催期間 | 2006/9/8(から1日開催) |
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| 講演論文情報詳細 | |
| 申込み研究会 | Reconfigurable Systems (RECONF) |
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| 本文の言語 | ENG |
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| サブタイトル（和） | |
| タイトル（英） | A Parametric Study of Packet-Switched FPGA Overlay Networks |
| サブタイトル（和） | |
| キーワード(1)（和/英） | / FPGA |
| 第 1 著者 氏名（和/英） | / Daihan WANG |
| 第 1 著者 所属（和/英） | Department of Information and Computer Science, Keio University |
| 発表年月日 | 2006-09-15 |
| 資料番号 | RECONF2006-32 |
| 巻番号（vol） | vol.106 |
| 号番号（no） | 247 |
| ページ範囲 | pp.- |
| ページ数 | 6 |
| 発行日 | |