| Presentation | 2006-09-15 Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The hardware multi-process execution is a technique to enhance throughput by dividing a reconfigurable device into several pieces and execute several processes in parallel. The hardware multi-process execution on Dynamically Reconfigurable Processor (DRP), which is a coarse grain reconfigurable processor developed by NEC Electronics, is implemented and evaluated with real applications, which can be divided into two categories: a single task like DCT or Viterbi decoder, and multi tasks like a JPEG encoder. An application is divided into small processes and implemented on a limited area of PE array. Inter-process communication is done through the embedded FIFO. Through the evaluation, the overhead of this modification is not so influenced to the performance, cost and power consumption. When the pipelined execution works well, the throughput is improved almost double. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware multi-process execution / DRP / single-process execution / performance / overhead |
| Paper # | RECONF2006-31 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/9/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor |
| Sub Title (in English) | |
| Keyword(1) | Hardware multi-process execution |
| Keyword(2) | DRP |
| Keyword(3) | single-process execution |
| Keyword(4) | performance |
| Keyword(5) | overhead |
| 1st Author's Name | Vu Manh Tuan |
| 1st Author's Affiliation | Keio University() |
| 2nd Author's Name | Yohei Hasegawa |
| 2nd Author's Affiliation | Keio University |
| 3rd Author's Name | Naohiro Katsura |
| 3rd Author's Affiliation | Keio University |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University |
| Date | 2006-09-15 |
| Paper # | RECONF2006-31 |
| Volume (vol) | vol.106 |
| Number (no) | 247 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |