講演名 | 2006-09-15 Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor , |
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抄録(英) | The hardware multi-process execution is a technique to enhance throughput by dividing a reconfigurable device into several pieces and execute several processes in parallel. The hardware multi-process execution on Dynamically Reconfigurable Processor (DRP), which is a coarse grain reconfigurable processor developed by NEC Electronics, is implemented and evaluated with real applications, which can be divided into two categories: a single task like DCT or Viterbi decoder, and multi tasks like a JPEG encoder. An application is divided into small processes and implemented on a limited area of PE array. Inter-process communication is done through the embedded FIFO. Through the evaluation, the overhead of this modification is not so influenced to the performance, cost and power consumption. When the pipelined execution works well, the throughput is improved almost double. |
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キーワード(英) | Hardware multi-process execution / DRP / single-process execution / performance / overhead |
資料番号 | RECONF2006-31 |
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研究会情報 | |
研究会 | RECONF |
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開催期間 | 2006/9/8(から1日開催) |
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申込み研究会 | Reconfigurable Systems (RECONF) |
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本文の言語 | ENG |
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タイトル(英) | Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor |
サブタイトル(和) | |
キーワード(1)(和/英) | / Hardware multi-process execution |
第 1 著者 氏名(和/英) | / Vu Manh Tuan |
第 1 著者 所属(和/英) | Keio University |
発表年月日 | 2006-09-15 |
資料番号 | RECONF2006-31 |
巻番号(vol) | vol.106 |
号番号(no) | 247 |
ページ範囲 | pp.- |
ページ数 | 6 |
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