| Presentation | 2006-09-14 How to Design FPGAs in a Nanometer Process Kazutoshi KOBAYASHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes how to design an FPGA LSI using a conventional digital-LSI design flow as a tutorial. Our research group designed several LSIs over the decade. Currently, our research topic is "variation-aware reconfigurable devices against process variations". We have fabricated two LSIs in a 90nm process provided by STARC. One is a fixed-wired LUT array and the other is a complete FPGA which has a functionality to measure variations. First we introduce an ordinal digital LSI design methodology, and the digital design flow dedicated for the STARC 90nm process. Finally the design methodology for the FPGA is shown in detail. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / LSI / nanometer process / process variation |
| Paper # | RECONF2006-26 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/9/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | How to Design FPGAs in a Nanometer Process |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | LSI |
| Keyword(3) | nanometer process |
| Keyword(4) | process variation |
| 1st Author's Name | Kazutoshi KOBAYASHI |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| Date | 2006-09-14 |
| Paper # | RECONF2006-26 |
| Volume (vol) | vol.106 |
| Number (no) | 246 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |