| Presentation | 2006-09-14 Yield Enhancement of FPGAs with Intra-die Variation Using Multiple Configuration Data Yohei MATSUMOTO, Masakazu HIOKI, Takashi KAWANAMI, Toshiyuki TSUTSUMI, Tadashi NAKAGAWA, Toshihiro SEKIGAWA, Hanpei KOIKE, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Scaling of the semiconductor process technology increases intra-die variations of device parameters such as threshold voltages of transistors, and causes degradation of performance yields of LSIs. In FPGAs, there is a proposed technique to avoid the intra-die variation and improve performance yield by designing circuit for each chMECPConsidering variation information measured before. On the other hand, such technique increases costs for testing and CAD run time, and is not possible in many cases. In this paper, we propose new technique to improve performance yield of FPGAs by choosing appropriate configuration from configurations generated to have probabilistically independent performances. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Configuration Data / Intra-Die Variation / Performance Yield |
| Paper # | RECONF2006-25 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/9/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Yield Enhancement of FPGAs with Intra-die Variation Using Multiple Configuration Data |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Configuration Data |
| Keyword(3) | Intra-Die Variation |
| Keyword(4) | Performance Yield |
| 1st Author's Name | Yohei MATSUMOTO |
| 1st Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST() |
| 2nd Author's Name | Masakazu HIOKI |
| 2nd Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST |
| 3rd Author's Name | Takashi KAWANAMI |
| 3rd Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST |
| 4th Author's Name | Toshiyuki TSUTSUMI |
| 4th Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST:Meiji University |
| 5th Author's Name | Tadashi NAKAGAWA |
| 5th Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST |
| 6th Author's Name | Toshihiro SEKIGAWA |
| 6th Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST |
| 7th Author's Name | Hanpei KOIKE |
| 7th Author's Affiliation | Electroinformatics Group, Nanoelectronics Research Institute, AIST |
| Date | 2006-09-14 |
| Paper # | RECONF2006-25 |
| Volume (vol) | vol.106 |
| Number (no) | 246 |
| Page | pp.pp.- |
| #Pages | 6 |
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