Presentation | 2006-09-14 Discussion of Memory-LSI Working as Reconfigurable Device Masanori YOSHIHARA, Tetsuo HIRONAKA, Masayuki SATO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Each function included in SoC are usually tested by the built in test circuits in the chip. Testing the SoC by the built in test circut is a effective way. but it has a disadvantage on chip cost. In our research we propose a memory-LSI working as reconfigurable device (MPLD) with alternating arrangement. In this paper, we designed a memory cell array for 32×4 bit 2port SRAM that are a part of MPLD by using HITACHI 0.18μm CMOS technology. As a result, we confirmed that the MPLD to function as a memory device and reconfigurable logic device, each at 500MHz and 900MHz. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | MPLD / Test Circuit / SoC / Memory |
Paper # | RECONF2006-24 |
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Committee | RECONF |
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Conference Date | 2006/9/7(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Discussion of Memory-LSI Working as Reconfigurable Device |
Sub Title (in English) | |
Keyword(1) | MPLD |
Keyword(2) | Test Circuit |
Keyword(3) | SoC |
Keyword(4) | Memory |
1st Author's Name | Masanori YOSHIHARA |
1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
2nd Author's Name | Tetsuo HIRONAKA |
2nd Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
3rd Author's Name | Masayuki SATO |
3rd Author's Affiliation | GENESIS TECHNOLOGY INC. |
Date | 2006-09-14 |
Paper # | RECONF2006-24 |
Volume (vol) | vol.106 |
Number (no) | 246 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |