| Presentation | 2006-09-14 A logic design technique using SRAM blocks Masayuki Sato, Hiroki Wakamatsu, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A low power on-board reconfigurable tester have been developed by using an FPGA. It is technically possible to configure test circuits on a chip by using FPGAs. In this study, we try to design reconfigurable logic circuits by using SRAMs. Firstly, we propose an alternating arrangement of SRAM blocks. Secondly, we propose a reconfigarable device with multi-port SRAMs. And then, we designed arithmetic circuits for experiments and we reduced SRAM block capacities. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable / reconfigurablablity / Test / ATE / Soc / arithmetic circuit |
| Paper # | RECONF2006-23 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2006/9/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A logic design technique using SRAM blocks |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable |
| Keyword(2) | reconfigurablablity |
| Keyword(3) | Test |
| Keyword(4) | ATE |
| Keyword(5) | Soc |
| Keyword(6) | arithmetic circuit |
| 1st Author's Name | Masayuki Sato |
| 1st Author's Affiliation | Genesis Technology Inc.() |
| 2nd Author's Name | Hiroki Wakamatsu |
| 2nd Author's Affiliation | Genesis Technology Inc. |
| Date | 2006-09-14 |
| Paper # | RECONF2006-23 |
| Volume (vol) | vol.106 |
| Number (no) | 246 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |