Presentation | 2006-09-14 Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays Ryo HIDAKA, Minoru WATANABE, Fuminori KOBAYASHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Optically Differential Reconfigurable Gate Arrays (ODRGAs) have been developed to realize a bit-by-bit reconfiguration capability. The ODRGA architecture allows to decrease the number of irradiations bits included in a context. On the other hand, the intensity of each bit of diffraction light from a holographic memory increases as decreasing the number of irradiation bits included in a context. This paper experimentally presents the advantage of the acceleration of reconfiguration speed and the reduction of power consumption in ODRGA architecture. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA / ODRGA / Holographic memory |
Paper # | RECONF2006-21 |
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Committee | RECONF |
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Conference Date | 2006/9/7(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays |
Sub Title (in English) | |
Keyword(1) | FPGA |
Keyword(2) | ODRGA |
Keyword(3) | Holographic memory |
1st Author's Name | Ryo HIDAKA |
1st Author's Affiliation | Kyushu Institute of Technology() |
2nd Author's Name | Minoru WATANABE |
2nd Author's Affiliation | Kyushu Institute of Technology |
3rd Author's Name | Fuminori KOBAYASHI |
3rd Author's Affiliation | Kyushu Institute of Technology |
Date | 2006-09-14 |
Paper # | RECONF2006-21 |
Volume (vol) | vol.106 |
Number (no) | 246 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |