Presentation | 2006-09-14 An Optically Reconfigurable Gate Array with manufacturing defect tolerance Ryo HIDAKA, Minoru WATANABE, Fuminori KOBAYASHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Recently, as VLSI process technologies are progressed, the defective fractions of VLSIs are more increased and the die sizes have to be smaller to decrease the number of defective chips. However, since the need for non-defective large die chips is increased day-by-day, we have developed optically reconfigurable gate arrays (ORGAs) with a parallel programming capablity. This paper presents a high manufacturing defect tolerance of the optically programmable architecture that combines high manufacturing defect tolerance-holographic memory onto an ORGA-VLSI with a parallel programming capablity. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGAs / ORGAs / Holographic memory |
Paper # | RECONF2006-20 |
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Committee | RECONF |
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Conference Date | 2006/9/7(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | An Optically Reconfigurable Gate Array with manufacturing defect tolerance |
Sub Title (in English) | |
Keyword(1) | FPGAs |
Keyword(2) | ORGAs |
Keyword(3) | Holographic memory |
1st Author's Name | Ryo HIDAKA |
1st Author's Affiliation | Kyushu Institute of Technology() |
2nd Author's Name | Minoru WATANABE |
2nd Author's Affiliation | Kyushu Institute of Technology |
3rd Author's Name | Fuminori KOBAYASHI |
3rd Author's Affiliation | Kyushu Institute of Technology |
Date | 2006-09-14 |
Paper # | RECONF2006-20 |
Volume (vol) | vol.106 |
Number (no) | 246 |
Page | pp.pp.- |
#Pages | 5 |
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