| Presentation | 2006/7/25 Mitigating The Performance Impact of Memory Integrity Verification by Exploiting Cache Decay Lines Takahiro SAKAGUCHI, Koji INOUE, Kazuaki MURAKAMI, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We focus on Memory Integrity Verificatoin that can detect memory corruption to the loading data by maintaining the state of the space of the memory for protection in a safe storage area. To waste on chip cache and the memory bandwidth, the execution of the Memory Integrity Verification gives a adverse effect to the processor performance. One of the factor of the performance decrease is causing competition between the data that the processor needs for the program execution and data for the Memory Integrity Verificatoin in cache. It happenes the memory access because of cache misses, and the processor performance decreases. To solve the issues, the data for Memory Integrity Verification is replaced in the cache line with low access frequency that is called Decay line. Therefore, it prevents evicting the data for program execution. We compare this method with past method, as a result, we can reduce the performance overhead by 23.8% on an average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High Security / Decay line |
| Paper # | DC2006-24 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2006/7/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Mitigating The Performance Impact of Memory Integrity Verification by Exploiting Cache Decay Lines |
| Sub Title (in English) | |
| Keyword(1) | High Security |
| Keyword(2) | Decay line |
| 1st Author's Name | Takahiro SAKAGUCHI |
| 1st Author's Affiliation | Graduate School of Infomation Science and Electrial Engineering, Kyushu University() |
| 2nd Author's Name | Koji INOUE |
| 2nd Author's Affiliation | Graduate School of Infomation Science and Electrial Engineering, Kyushu University:PRESTO, Japan Science and Technology Agency |
| 3rd Author's Name | Kazuaki MURAKAMI |
| 3rd Author's Affiliation | Graduate School of Infomation Science and Electrial Engineering, Kyushu University |
| Date | 2006/7/25 |
| Paper # | DC2006-24 |
| Volume (vol) | vol.106 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |