Presentation | 2006/7/25 Design of Radix Converters Using Arithmetic Decomposition Yukihiro IGUCHI, Tsutomu SASAO, Munehiro MATSUURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Radix converter / Multiple valued logic / LUT cascades / FPGA |
Paper # | DC2006-23 |
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Committee | DC |
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Conference Date | 2006/7/25(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design of Radix Converters Using Arithmetic Decomposition |
Sub Title (in English) | |
Keyword(1) | Radix converter |
Keyword(2) | Multiple valued logic |
Keyword(3) | LUT cascades |
Keyword(4) | FPGA |
1st Author's Name | Yukihiro IGUCHI |
1st Author's Affiliation | Department of Computer Scienece, Meiji University() |
2nd Author's Name | Tsutomu SASAO |
2nd Author's Affiliation | Department of Computer Scienece and Electronics, Kyushu Institute of Technology |
3rd Author's Name | Munehiro MATSUURA |
3rd Author's Affiliation | Department of Computer Scienece and Electronics, Kyushu Institute of Technology |
Date | 2006/7/25 |
Paper # | DC2006-23 |
Volume (vol) | vol.106 |
Number (no) | 198 |
Page | pp.pp.- |
#Pages | 6 |
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