Presentation 2006/7/25
Consideration of Time Redundancy Processor with the Tolerance to Transient Faults
Makoto KIMURA, Masayuki ARAI, Satoshi FUKUMOTO, Kazuhiko IWASAKI,
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Abstract(in English) With the advancements of semiconductor manufacturing technology into deep-submicron process, accompanied by higher frequency and lower power consumption, transient faults have become to affect to digital circuits more seriously. In this paper, we discussed about a time redundancy processor aiming at tolerating transient faults caused by electromagnetic waves. First, we evaluated the effects of electromagnetic waves caused by discharge of a capacitor to a sequential circuit which is implemented on an FPGA, and then we established the fault model according to the experimental results. Next, we designed the time redundancy processor that can tolerate the established fault model. We implemented the proposed processor on an FPGA and evaluated its resistance property to transient faults.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Transient faults / Electromagnetic wave / Soft error / Time redundancy / FPGA
Paper # DC2006-15
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Committee DC
Conference Date 2006/7/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Consideration of Time Redundancy Processor with the Tolerance to Transient Faults
Sub Title (in English)
Keyword(1) Transient faults
Keyword(2) Electromagnetic wave
Keyword(3) Soft error
Keyword(4) Time redundancy
Keyword(5) FPGA
1st Author's Name Makoto KIMURA
1st Author's Affiliation Tokyo Metropolitan University()
2nd Author's Name Masayuki ARAI
2nd Author's Affiliation Tokyo Metropolitan University
3rd Author's Name Satoshi FUKUMOTO
3rd Author's Affiliation Tokyo Metropolitan University
4th Author's Name Kazuhiko IWASAKI
4th Author's Affiliation Tokyo Metropolitan University
Date 2006/7/25
Paper # DC2006-15
Volume (vol) vol.106
Number (no) 198
Page pp.pp.-
#Pages 6
Date of Issue