Presentation 2006/7/25
A Soft-Error Tolerant Look-Up Table Cascade Emulator
Hiroki NAKAHARA, Tsutomu SASAO,
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Abstract(in English) An LUT cascade emulator realizes an arbitrary sequential circuit. We convert the combinational part into multiple LUT cascades, and store LUT(cell) data into a memory in the LUT cascade emulator. It evaluates multi-output logic functions by reading cell data sequentially. To improve torelance to soft errors, we encode cell data stored in the memory by error correcting codes. Also, we add an error-correcting circuit. A scanning circuit periodically scans the memory. When it detects a soft error, it remove the error by write-backing the correct data into the memory. To avoid the soft error for flip-flops, we employ a TMR (Triple Module Redundancy) technique. Our method detects the soft errors in a single bit. Also, the mission time of our method is more than 1000x of an ordinary LUT cascade emulator.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) LUT cascade / Reconfigurable architecture / Self-adaptability architecture / Functional decomposition
Paper # DC2006-14
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Committee DC
Conference Date 2006/7/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Soft-Error Tolerant Look-Up Table Cascade Emulator
Sub Title (in English)
Keyword(1) LUT cascade
Keyword(2) Reconfigurable architecture
Keyword(3) Self-adaptability architecture
Keyword(4) Functional decomposition
1st Author's Name Hiroki NAKAHARA
1st Author's Affiliation Department of Comoputer Science and Electronics, Kyushu Institute of Technology()
2nd Author's Name Tsutomu SASAO
2nd Author's Affiliation Department of Comoputer Science and Electronics, Kyushu Institute of Technology
Date 2006/7/25
Paper # DC2006-14
Volume (vol) vol.106
Number (no) 198
Page pp.pp.-
#Pages 5
Date of Issue