Presentation 2006/7/25
Evaluation of Terrestrial-Neutron Induced Single Event of Memory Devices : An Outlook for Logic Devices
Yasuo YAHAGI, Eishi IBE, Hironaru YAMAGUCHI, Hideaki KAMEYAMA, Yasuyuki SAITO, Takashi AKIOKA, Shigehisa YAMAMOTO, Mitsumori HIDAKA, Atsushi SAITO,
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Abstract(in English) Scaling of semiconductor devices down to sub-100nm technologies has raised a problem that the impact of neutron-induced errors especially on combinational logic circuits is becoming more critical. Concerning memory devices, the international standardization of test procedure for soft errors has been achieved though new neutron-induced error modes are being reported. On the other hand, various challenges on characterizing the susceptibility of combinational logic circuits to terrestrial neutron have been attempted and a standard soft-error evaluation method of logic circuits has not been achieved yet due to its complication. In this paper, test methods of terrestrial-neutron soft-errors of memory devices including field test, accelerated test by using high energy particle accelerators, and simulations are explained, and a brief description of the soft-error evaluation of combinational logic circuits is given.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) cosmic rays / neutron / soft-error / single event / SEU / SET / SEL / memory / combinational logic
Paper # DC2006-13
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Committee DC
Conference Date 2006/7/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of Terrestrial-Neutron Induced Single Event of Memory Devices : An Outlook for Logic Devices
Sub Title (in English)
Keyword(1) cosmic rays
Keyword(2) neutron
Keyword(3) soft-error
Keyword(4) single event
Keyword(5) SEU
Keyword(6) SET
Keyword(7) SEL
Keyword(8) memory
Keyword(9) combinational logic
1st Author's Name Yasuo YAHAGI
1st Author's Affiliation Production Engineering Research Laboratory, Hitachi, Ltd.()
2nd Author's Name Eishi IBE
2nd Author's Affiliation Production Engineering Research Laboratory, Hitachi, Ltd.
3rd Author's Name Hironaru YAMAGUCHI
3rd Author's Affiliation Production Engineering Research Laboratory, Hitachi, Ltd.
4th Author's Name Hideaki KAMEYAMA
4th Author's Affiliation Renesas Technology Corp.
5th Author's Name Yasuyuki SAITO
5th Author's Affiliation Renesas Technology Corp.
6th Author's Name Takashi AKIOKA
6th Author's Affiliation Renesas Technology Corp.
7th Author's Name Shigehisa YAMAMOTO
7th Author's Affiliation Renesas Technology Corp.
8th Author's Name Mitsumori HIDAKA
8th Author's Affiliation Elpida Memory Inc.
9th Author's Name Atsushi SAITO
9th Author's Affiliation Elpida Memory Inc.
Date 2006/7/25
Paper # DC2006-13
Volume (vol) vol.106
Number (no) 198
Page pp.pp.-
#Pages 6
Date of Issue