Presentation 2006/6/26
The Guideline of Tolerable Vth Fluctuation for MCML (MOS Current Mode Logic) Inverter Circuit(Session 8A Silicon Devices V)
Hyoung-jun NA, Maki SUEMITSU, Tetsuo ENDOH,
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Abstract(in English) In this paper, the guideline of tolerable threshold voltage (Vth) fluctuation of MOS Current Mode Logic (MCML) was presented by using HSPICE simulations. The dependence of bias offset voltage ΔV_B, that is defined as (base voltage of output waveform) - (base voltage of input wave form), on Vth fluctuation of NMOS and PMOS was investigated. The tolerable Vth fluctuation of NMOS and PMOS that satisfies ΔV_B≦50mV and ΔV_B≦100mV in MCML inverter was shown, respectively. With using this proposed guideline of tolerable Vth fluctuation, we clarified that in order to improve the stability of MCML inverter, it is effective to suppress the Vth fluctuation of NMOS.
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Keyword(in English) MCML / Vth Fluctuation / Stability / HSPICE Simulation / NMOS / PMOS
Paper # ED2006-103,SDM2006-111
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Committee SDM
Conference Date 2006/6/26(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The Guideline of Tolerable Vth Fluctuation for MCML (MOS Current Mode Logic) Inverter Circuit(Session 8A Silicon Devices V)
Sub Title (in English)
Keyword(1) MCML
Keyword(2) Vth Fluctuation
Keyword(3) Stability
Keyword(4) HSPICE Simulation
Keyword(5) NMOS
Keyword(6) PMOS
1st Author's Name Hyoung-jun NA
1st Author's Affiliation Center for Interdisciplinary Research, Tohoku University()
2nd Author's Name Maki SUEMITSU
2nd Author's Affiliation Center for Interdisciplinary Research, Tohoku University
3rd Author's Name Tetsuo ENDOH
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
Date 2006/6/26
Paper # ED2006-103,SDM2006-111
Volume (vol) vol.106
Number (no) 138
Page pp.pp.-
#Pages 4
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