Presentation 2006/6/26
Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance(Session 7B Compound Semiconductor Devices III)
Kozo MAKIYAMA, Tsuyoshi TAKAHASHI, Toshihide SUZUKI, Toshihiro OHKI, Naoki KARA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We developed a process technology to remove parasitic capacitance around gate electrode originated in interconnecting layer of circuits. This process enabled us to increase the operating speed of integrated circuit, and we reported 90 GHz operation of a static T-FF circuit. We evaluated S-parameter precisely and confirmed the effect of reducing parasitic capacitance. This process technology has potential to further improve cutoff frequency, f_T, by further reducing the length of the gate electrode.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) CAVE / parasitic capacitance / circuit-speed
Paper # ED2006-96,SDM2006-104
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Conference Information
Committee SDM
Conference Date 2006/6/26(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance(Session 7B Compound Semiconductor Devices III)
Sub Title (in English)
Keyword(1) CAVE
Keyword(2) parasitic capacitance
Keyword(3) circuit-speed
1st Author's Name Kozo MAKIYAMA
1st Author's Affiliation Fujitsu Limited()
2nd Author's Name Tsuyoshi TAKAHASHI
2nd Author's Affiliation Fujitsu Limited
3rd Author's Name Toshihide SUZUKI
3rd Author's Affiliation Fujitsu Limited
4th Author's Name Toshihiro OHKI
4th Author's Affiliation Fujitsu Laboratories Ltd.
5th Author's Name Naoki KARA
5th Author's Affiliation Fujitsu Limited
Date 2006/6/26
Paper # ED2006-96,SDM2006-104
Volume (vol) vol.106
Number (no) 138
Page pp.pp.-
#Pages 6
Date of Issue