| Presentation | 2006/6/26 High Current, High Power, and High Linearity Ohmic Recess InGaP/InGaAs Doped Channel FETs(Session 7B Compound Semiconductor Devices III) Feng-Tso Chien, Chien-Liang Chan, Chien-Nan Liao, Jin-Mu Yin, Hsien-Chin Chiu, Feng Tsun Chien, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Performance of contact resistance, dc, rf, microwave power, and device linearity characteristics between proposed partial drain/source ohmic recess InGaP/InGaAs/GaAs doped-channel FETs (OR-DCFETs) and the conventional doped-channel FETs (DCFETs) are compared in this research. The proposed ohmic recess process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer, and therefore improves the device performance in terms of dc, rf, source resistance as well as power characteristics. Owing to a lower source and drain resistances characteristic, OR-DCFETs demonstrated a high device current, high power-added efficiency (PAE), and better device linearity, which are very important for microwave power applications. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | InGaP/InGaAs / doped-channel EFTs / source and drain resistance / device linearity / PAE |
| Paper # | ED2006-95,SDM2006-103 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2006/6/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Current, High Power, and High Linearity Ohmic Recess InGaP/InGaAs Doped Channel FETs(Session 7B Compound Semiconductor Devices III) |
| Sub Title (in English) | |
| Keyword(1) | InGaP/InGaAs |
| Keyword(2) | doped-channel EFTs |
| Keyword(3) | source and drain resistance |
| Keyword(4) | device linearity |
| Keyword(5) | PAE |
| 1st Author's Name | Feng-Tso Chien |
| 1st Author's Affiliation | Dept. of Electronic Engineering, Feng Chia University() |
| 2nd Author's Name | Chien-Liang Chan |
| 2nd Author's Affiliation | Dept. of Electronic Engineering, Feng Chia University |
| 3rd Author's Name | Chien-Nan Liao |
| 3rd Author's Affiliation | Dept. of Electronic Engineering, Feng Chia University |
| 4th Author's Name | Jin-Mu Yin |
| 4th Author's Affiliation | Dept. of Electronic Engineering, Feng Chia University |
| 5th Author's Name | Hsien-Chin Chiu |
| 5th Author's Affiliation | Dept. of Electronic Engineering, Chang Gung University |
| 6th Author's Name | Feng Tsun Chien |
| 6th Author's Affiliation | Dept. of Electronics Engineering, National Chiao Tung University |
| Date | 2006/6/26 |
| Paper # | ED2006-95,SDM2006-103 |
| Volume (vol) | vol.106 |
| Number (no) | 138 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |