SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)

Presentation	2006/6/26 SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006) InSoo Jung, Byeong-Chan Lee, Deok-Hyung Lee, Sun-Ghil Lee, Jong-Wook Lee, Siyoung Choi, U-In Chung, Joo Tae Moon,
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Abstract(in English)	Recently, the recessed SiGe source and drain (SD) structure is widely applied for boosting the performance of pMOS transistor due to the enhanced hole mobility. In this study, the SiGe SD structure was embedded in the peripheral pMOS transistor of DRAM for the first time. We used about 20 at.% of Ge contents for the SiGe SD layer and more than 40% of I_ improvement in the pMOS transistor was shown without any degradation of the peripheral nMOS transistor properties. The low sheet resistance of the SiGe layer and the contact resistance between metal and SiGe layer as well as the compressive stress in the channel region are believed to be the origin of the performance gain in the pMOS. It was also confirmed that the Si elevated SD structure after the SiGe SD formation reduced the performance enhancement in the pMOS, which was also shown in the simulated results..
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	DRAM / SiGe source and drain / Si elevated source and drain / selective epitaxial growth (SEG) / Stress
Paper #	ED2006-89,SDM2006-97
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Conference Information
Committee	SDM
Conference Date	2006/6/26(1days)
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Paper Information
Registration To	Silicon Device and Materials (SDM)
Language	ENG
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
Sub Title (in English)
Keyword(1)	DRAM
Keyword(2)	SiGe source and drain
Keyword(3)	Si elevated source and drain
Keyword(4)	selective epitaxial growth (SEG)
Keyword(5)	Stress
1st Author's Name	InSoo Jung
1st Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.()
2nd Author's Name	Byeong-Chan Lee
2nd Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
3rd Author's Name	Deok-Hyung Lee
3rd Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
4th Author's Name	Sun-Ghil Lee
4th Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
5th Author's Name	Jong-Wook Lee
5th Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
6th Author's Name	Siyoung Choi
6th Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
7th Author's Name	U-In Chung
7th Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
8th Author's Name	Joo Tae Moon
8th Author's Affiliation	Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
Date	2006/6/26
Paper #	ED2006-89,SDM2006-97
Volume (vol)	vol.106
Number (no)	138
Page	pp.pp.-
#Pages	4
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