| Presentation | 2006/6/26 A Novel Power MOSFET Structure with Shallow Junction Dual Well Design(Session 6B Power Devices,AWAD2006) Feng-Tso Chien, Chien-Nan Liao, Yei-Long Tsai, Ching-Ling Cheng, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Vertical Power MOSFETs are widely designed by deep well structures for breakdown requirement. In this study, we proposed, fabricated, and analyzed a "shallow dual well" structure Power MOSFET, which utilize an n-well to cover the conventional p-well. The cell density can be increased 351%. The increased cell density leads to improved gate charge and on resistance performances about 66.5% and 15.8% without sacrificing the device breakdown owing to a shallow junction design. In addition, with the dual well structure design, the breakdown point will occur at the center of the well. Therefore, the capability of avalanche energy can be improved about 1.9 times than the tradition well structure. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power MOSFET / VDMOSFET / shallow dual well / avalanche breakdown |
| Paper # | ED2006-85,SDM2006-93 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2006/6/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Novel Power MOSFET Structure with Shallow Junction Dual Well Design(Session 6B Power Devices,AWAD2006) |
| Sub Title (in English) | |
| Keyword(1) | Power MOSFET |
| Keyword(2) | VDMOSFET |
| Keyword(3) | shallow dual well |
| Keyword(4) | avalanche breakdown |
| 1st Author's Name | Feng-Tso Chien |
| 1st Author's Affiliation | Department of Electronic Engineering, Feng Chia University() |
| 2nd Author's Name | Chien-Nan Liao |
| 2nd Author's Affiliation | Department of Electronic Engineering, Feng Chia University |
| 3rd Author's Name | Yei-Long Tsai |
| 3rd Author's Affiliation | R&D DEPT, Chino-Excel Technology Corp. |
| 4th Author's Name | Ching-Ling Cheng |
| 4th Author's Affiliation | R&D DEPT, Chino-Excel Technology Corp. |
| Date | 2006/6/26 |
| Paper # | ED2006-85,SDM2006-93 |
| Volume (vol) | vol.106 |
| Number (no) | 138 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |