Presentation | 2006/6/26 High-k/Metal Gate Stack for Advanced CMOS(Session 4 Silicon Devices II,AWAD2006) Yasuo NARA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices. In this presentation, gate stack technology using high-k gate dielectrics and metal gate will be discussed, and recent achievements of these technologies will be reviewed. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | CMOS / Gate stack / Gate Dielectrics / High-k Gate Dielectrics / Metal gate |
Paper # | ED2006-74,SDM2006-82 |
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Conference Information | |
Committee | SDM |
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Conference Date | 2006/6/26(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | High-k/Metal Gate Stack for Advanced CMOS(Session 4 Silicon Devices II,AWAD2006) |
Sub Title (in English) | |
Keyword(1) | CMOS |
Keyword(2) | Gate stack |
Keyword(3) | Gate Dielectrics |
Keyword(4) | High-k Gate Dielectrics |
Keyword(5) | Metal gate |
1st Author's Name | Yasuo NARA |
1st Author's Affiliation | Semiconductor Leading Edge Technologies, Inc.() |
Date | 2006/6/26 |
Paper # | ED2006-74,SDM2006-82 |
Volume (vol) | vol.106 |
Number (no) | 138 |
Page | pp.pp.- |
#Pages | 4 |
Date of Issue |