Presentation 2006/6/26
InP HEMT Technology for High-Speed Logic and Communications(Session 2 Compound Semiconductor Devices I,AWAD2006)
Tetsuya SUEMITSU, Masami TOKUMITSU,
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Abstract(in English) As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) HEMT / InP / Cutoff frequency / OEIC
Paper # ED2006-64,SDM2006-72
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Conference Information
Committee SDM
Conference Date 2006/6/26(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) InP HEMT Technology for High-Speed Logic and Communications(Session 2 Compound Semiconductor Devices I,AWAD2006)
Sub Title (in English)
Keyword(1) HEMT
Keyword(2) InP
Keyword(3) Cutoff frequency
Keyword(4) OEIC
1st Author's Name Tetsuya SUEMITSU
1st Author's Affiliation NTT Photonics Laboratories, NTT Corporation()
2nd Author's Name Masami TOKUMITSU
2nd Author's Affiliation NTT Photonics Laboratories, NTT Corporation
Date 2006/6/26
Paper # ED2006-64,SDM2006-72
Volume (vol) vol.106
Number (no) 138
Page pp.pp.-
#Pages 5
Date of Issue