Presentation 2006-07-28
About error probability of the NAND circuit which I used four beam splitter gates and an FTM gate for
Ren Furukoshi, Noboru Watanabe,
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Abstract(in English) In logic gates becoming the basics of a current computer, there are problems such as non-reversibility, a loss of information of a calculation. In addition, a loss of this information generates transaction speed and a problem of a limit of degree of integration. Holding down the loss of the information with the non reversibility of at this calculation, those where it is expected that it improves throughput, are the quantum computer. About I use quantum logic gate by this report, and realizing real logic gate, I make an NAND circuit with FTM gate, two kinds of four beam splitter gates as an example and calculate error probability about each.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FTM gate and four beam splitter gates / error probability
Paper # IT2006-36
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Committee IT
Conference Date 2006/7/21(1days)
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Registration To Information Theory (IT)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) About error probability of the NAND circuit which I used four beam splitter gates and an FTM gate for
Sub Title (in English)
Keyword(1) FTM gate and four beam splitter gates
Keyword(2) error probability
1st Author's Name Ren Furukoshi
1st Author's Affiliation Dept of information science, Faculty of Science and engineering, Tokyo University of Science()
2nd Author's Name Noboru Watanabe
2nd Author's Affiliation Dept of information science, Faculty of Science and engineering, Tokyo University of Science
Date 2006-07-28
Paper # IT2006-36
Volume (vol) vol.106
Number (no) 185
Page pp.pp.-
#Pages 6
Date of Issue