| Presentation | 2006-07-20 Double-Size Montgomery Multiplication of a Crypto-Coprocessor Masayuki YOSHINO, Katsuyuki OKEYA, Camille VUILLAUME, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present a novel approach for computing 2n-bit Montgomery multiplications with n-bit hardware Montgomery multipliers. Smartcards are usually equipped with such hardware Montgomery multipliers; however, due to progresses in factoring algorithms, the recommended bit length of public-key schemes such as RSA is steadily increasing, making the hardware quickly obsolete. Thanks to our double-size technique, one can re-use the existing hardware while keeping pace with the latest security requirements. Unlike the other double-size techniques which rely on classical n-bit modular multipliers, our idea is tailored to take advantage of n-bit Montgomery multipliers. Thus, our technique increases the perenniality of existing products without compromises in terms of security. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Montgomery multiplication / double-size technique / RSA / crypto-coprocessor / smartcard |
| Paper # | ISEC2006-21,SITE2006-18 |
| Date of Issue |
| Conference Information | |
| Committee | SITE |
|---|---|
| Conference Date | 2006/7/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Social Implications of Technology and Information Ethics (SITE) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Double-Size Montgomery Multiplication of a Crypto-Coprocessor |
| Sub Title (in English) | |
| Keyword(1) | Montgomery multiplication |
| Keyword(2) | double-size technique |
| Keyword(3) | RSA |
| Keyword(4) | crypto-coprocessor |
| Keyword(5) | smartcard |
| 1st Author's Name | Masayuki YOSHINO |
| 1st Author's Affiliation | Hitachi, Ltd., Systems Development Laboratory() |
| 2nd Author's Name | Katsuyuki OKEYA |
| 2nd Author's Affiliation | Hitachi, Ltd., Systems Development Laboratory |
| 3rd Author's Name | Camille VUILLAUME |
| 3rd Author's Affiliation | Hitachi, Ltd., Systems Development Laboratory |
| Date | 2006-07-20 |
| Paper # | ISEC2006-21,SITE2006-18 |
| Volume (vol) | vol.106 |
| Number (no) | 174 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |