Presentation 2006-07-28
Simultaneous Calibration of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits
Zheng LIU, Masanori FURUTA, Shoji KAWAHITO,
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Abstract(in English) The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. This research points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew calibration. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) RC mismatch / clock skew / time-interleaved ADCs / calibration
Paper # ICD2006-78
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Committee ICD
Conference Date 2006/7/20(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Simultaneous Calibration of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits
Sub Title (in English)
Keyword(1) RC mismatch
Keyword(2) clock skew
Keyword(3) time-interleaved ADCs
Keyword(4) calibration
1st Author's Name Zheng LIU
1st Author's Affiliation Graduate School of Electronic Science and Technology, Shizuoka University()
2nd Author's Name Masanori FURUTA
2nd Author's Affiliation Research Institute of Electronics, Shizuoka University
3rd Author's Name Shoji KAWAHITO
3rd Author's Affiliation Research Institute of Electronics, Shizuoka University
Date 2006-07-28
Paper # ICD2006-78
Volume (vol) vol.106
Number (no) 189
Page pp.pp.-
#Pages 6
Date of Issue