Presentation 2006-07-27
A study on the multi-bit-pipelined A/D converter
Hiroki ENDOU, Masaya MIYAHARA, Akira MATSUZAWA,
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Abstract(in English) We have studied on the multi-bit pipeline A/D converter from the view pints of needed OP amp gain, needed capacitance, linearity, and the relation between operating current and conversion frequency. Better DNL will be expected, even if using small capacitance compared with a conventional 1.5 bit pipeline ADC. INL and needed capacitance value calculated by thermal noise analysis will be independent of the resolution for the unit conversion stage. Simulated maximum conversion frequency of the multi-bit pipelined ADC is slightly higher than that of the 1.5 bit pipelined ADC in low power region where the parasitic capacitances are sufficiently smaller than the signal capacitances.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Analog to digital converter / pipeline operation / multi-bit conversion / low power technology / high speed technology
Paper # ICD2006-63
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Committee ICD
Conference Date 2006/7/20(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study on the multi-bit-pipelined A/D converter
Sub Title (in English)
Keyword(1) Analog to digital converter
Keyword(2) pipeline operation
Keyword(3) multi-bit conversion
Keyword(4) low power technology
Keyword(5) high speed technology
1st Author's Name Hiroki ENDOU
1st Author's Affiliation Department of Physical Electronics, Tokyo Institute of Technology()
2nd Author's Name Masaya MIYAHARA
2nd Author's Affiliation Department of Physical Electronics, Tokyo Institute of Technology
3rd Author's Name Akira MATSUZAWA
3rd Author's Affiliation Department of Physical Electronics, Tokyo Institute of Technology
Date 2006-07-27
Paper # ICD2006-63
Volume (vol) vol.106
Number (no) 189
Page pp.pp.-
#Pages 6
Date of Issue