Presentation 2006-07-27
A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques
Kazutaka HONDA, Masanori FURUTA, Shoji KAWAHITO,
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Abstract(in English) This paper describes a low power low distortion pipeline ADC with 1.0V supply voltage. A 10b 100MSample/s A/D converter using capacitance coupling class-AB amplifier consumes only 30mW in a 90nm digital CMOS technology. The capacitance coupling S/H stage suppresses the distortion caused by the insufficient gate-source voltage of sampling switches due to a low supply voltage. The SNDR and the SFDR at 100MHz sampling are 53.8 dB and 71.2 dB, respectively.
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Keyword(in English) Low power / Low voltage / pipeline A/D converter / class-AB amplifier / capacitance coupling
Paper # ICD2006-62
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Committee ICD
Conference Date 2006/7/20(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques
Sub Title (in English)
Keyword(1) Low power
Keyword(2) Low voltage
Keyword(3) pipeline A/D converter
Keyword(4) class-AB amplifier
Keyword(5) capacitance coupling
1st Author's Name Kazutaka HONDA
1st Author's Affiliation Graduate school of Electronics Science and Technology, Shizuoka University()
2nd Author's Name Masanori FURUTA
2nd Author's Affiliation Reseach Institute of Electronics, Shizuoka University
3rd Author's Name Shoji KAWAHITO
3rd Author's Affiliation Reseach Institute of Electronics, Shizuoka University
Date 2006-07-27
Paper # ICD2006-62
Volume (vol) vol.106
Number (no) 189
Page pp.pp.-
#Pages 6
Date of Issue