| Presentation | 2006-07-06 Implementation of the Fully Asynchronous SFQ Microprocessor SCRAM2 Yusuke NOBUMORI, Kazunori NAKAMIYA, Takanobu NISHIGAI, Nobuyuki YOSHIKAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Pico-second timing design in the chip-level clock distribution of synchronous RSFQ digital systems is very difficult and time consuming. In order to make the timing design easy and to investigate the asynchronous timing design, we have been developing a fully asynchronous RSFQ microprocessor named SCRAM2, as a test vehicle. In the SCRAM2, the data-driven self-timed (DDST) architecture is used for the design of circuit blocks, and a hand shaking protocol is used for controlling the data flow between the circuit blocks. We have also enhanced the performance of the hand shaking system based on a delay optimization model. In this paper, we have designed, implemented and tested SCRAM2 microprocessor. The correct operations of all circuit components of SCRAM2 were confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ / Asynchronous design / Microprocessor / Pipeline / Handshaking / DDST / BDD |
| Paper # | SCE2006-13 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2006/6/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of the Fully Asynchronous SFQ Microprocessor SCRAM2 |
| Sub Title (in English) | |
| Keyword(1) | SFQ |
| Keyword(2) | Asynchronous design |
| Keyword(3) | Microprocessor |
| Keyword(4) | Pipeline |
| Keyword(5) | Handshaking |
| Keyword(6) | DDST |
| Keyword(7) | BDD |
| 1st Author's Name | Yusuke NOBUMORI |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Kazunori NAKAMIYA |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Takanobu NISHIGAI |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Nobuyuki YOSHIKAWA |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| Date | 2006-07-06 |
| Paper # | SCE2006-13 |
| Volume (vol) | vol.106 |
| Number (no) | 139 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |