| Presentation | 2006/6/29 Performance comparison of LMS, RLS and QRD-RLS algorithm by FPGA Implementation Yoshiaki YOKOYAMA, Hirokazu OBA, Minseok KIM, Hiroyuki ARAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Minimum Mean Square Error (MMSE) Adaptive Array Antenna is an effective technique to achieve high-speed mobile communication system. MMSE suppresses the interference and delayed waves by steering null direction to them, and detects the desired signal by forming the main-lobe to the desired wave. There are some well-known optimization techniques to obtain the optimum weights, RLS (Recursive Least Squares) algorithm is known as fast convergence property than LMS (Least Mean Square) algorithm. However, the complexity increases in proportion to the square of the number of array elements. A systolic array processor computes the QRD-RLS algorithm based on Givens rotation using of high order of parallelism and pipeline architecture, and it can reduce the processing time needed by RLS algorithm. This report presents FPGA implementation of LMS, RLS, QRD-RLS algorithm and evaluates gate usages, convergence characteristics at actual processing time and bit dependency with fixed-point computation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | adaptive array antenna / NLMS / RLS / QRD-RLS / RLS systolic array / FPGA implementation |
| Paper # | A・P2006-51 |
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| Conference Information | |
| Committee | AP |
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| Conference Date | 2006/6/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Antennas and Propagation (A・P) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance comparison of LMS, RLS and QRD-RLS algorithm by FPGA Implementation |
| Sub Title (in English) | |
| Keyword(1) | adaptive array antenna |
| Keyword(2) | NLMS |
| Keyword(3) | RLS |
| Keyword(4) | QRD-RLS |
| Keyword(5) | RLS systolic array |
| Keyword(6) | FPGA implementation |
| 1st Author's Name | Yoshiaki YOKOYAMA |
| 1st Author's Affiliation | Graduate School of Engineering, Yokohama National University() |
| 2nd Author's Name | Hirokazu OBA |
| 2nd Author's Affiliation | Graduate School of Engineering, Yokohama National University |
| 3rd Author's Name | Minseok KIM |
| 3rd Author's Affiliation | Brains Corporation |
| 4th Author's Name | Hiroyuki ARAI |
| 4th Author's Affiliation | Graduate School of Engineering, Yokohama National University |
| Date | 2006/6/29 |
| Paper # | A・P2006-51 |
| Volume (vol) | vol.106 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |