| Presentation | 2006/6/16 A Functional Unit Design of Motion Estimator on DSP for H.264/AVC Encoding Toyokazu TAKAHASHI, Shunitsu KOHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The improved coding efficiency in H.264/AVC comes from higher computational complexity. Most of that is related to motion estimation. Some new features, such as multiple reference frame, variable block size motion compensation and quarter-pel accuracy motion compensation have been adopted to improve coding peformance, however they would increase the processing time. On the other hand, to speed up motion estimation, many architectures that can implement integer-pel motion estimation have also been proposed. However, it's difficult to improve the processing performance of such architectures in memory bandwidth restricted architecture like a DSP datapath, due to the irregular memory access. In this paper, we propose an integer-pel motion estimator on DSP that adopts pixel subsampling technique to reduce hardware cost. In addition, we modify subsampling pattern from commonly used chessboad-like pattern to vertical-striped pattern, which is able to speed up motion estimation by reducing memory access cycles. The proposed architecture can process 86.5 CIF frames per second at 200MHz operating frequency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | H.264/AVC / motion estimation / full search block matching / DSP / VLSI architecture |
| Paper # | CAS2006-10,VID2006-23,SIP2006-33 |
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| Committee | SIP |
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| Conference Date | 2006/6/16(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Signal Processing (SIP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Functional Unit Design of Motion Estimator on DSP for H.264/AVC Encoding |
| Sub Title (in English) | |
| Keyword(1) | H.264/AVC |
| Keyword(2) | motion estimation |
| Keyword(3) | full search block matching |
| Keyword(4) | DSP |
| Keyword(5) | VLSI architecture |
| 1st Author's Name | Toyokazu TAKAHASHI |
| 1st Author's Affiliation | Dept. of Computer Science, Waseda University() |
| 2nd Author's Name | Shunitsu KOHARA |
| 2nd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science, Waseda University |
| Date | 2006/6/16 |
| Paper # | CAS2006-10,VID2006-23,SIP2006-33 |
| Volume (vol) | vol.106 |
| Number (no) | 116 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |