Presentation 2006/6/9
A Study on Fast Power Line Network with LDPC
Yutaka MATSUYAMA, Yoshiki KAMI, Shingo YOSHIZAWA, Yoshikazu MIYANAGA,
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Abstract(in English) In this study, we apply a low-density parity check (LDPC) code into the error correcting of a high-speed PLC system for reliable communication. As conventional methods in LDPC, a QC code has the best BER performance which is near Shannon limit. The proposed PLC system utilizes a QC code and sum-product algorithm (SPA) suitable for a multiple modulation. The PLC system requirements for achieving a 200M-bps throughput are considered in a view of complexity in LDPC. In the simulation, we compare the three types of LDPC codes with the convolutional code in terms of BER performance and discuss their simulation results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) PLC / LDPC / Quasi-Cyclic codes / 256QAM / Sum-Product decoding
Paper # SIS2006-13
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Conference Date 2006/6/9(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Study on Fast Power Line Network with LDPC
Sub Title (in English)
Keyword(1) PLC
Keyword(2) LDPC
Keyword(3) Quasi-Cyclic codes
Keyword(4) 256QAM
Keyword(5) Sum-Product decoding
1st Author's Name Yutaka MATSUYAMA
1st Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University()
2nd Author's Name Yoshiki KAMI
2nd Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
3rd Author's Name Shingo YOSHIZAWA
3rd Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
4th Author's Name Yoshikazu MIYANAGA
4th Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
Date 2006/6/9
Paper # SIS2006-13
Volume (vol) vol.106
Number (no) 96
Page pp.pp.-
#Pages 6
Date of Issue