| Presentation | 2006-06-09 Optimal Memory Allocation for Image Processor Masanori HARIYAMA, Yasuhiro KOBAYASHI, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents an efficient memory allocation to minimize the number of memory modules and processing elements with a parallel access capability based on regularity of window-type image processing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis / memory allocation / scheduling / image processing |
| Paper # | ICD2006-57 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/6/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimal Memory Allocation for Image Processor |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | memory allocation |
| Keyword(3) | scheduling |
| Keyword(4) | image processing |
| 1st Author's Name | Masanori HARIYAMA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Yasuhiro KOBAYASHI |
| 2nd Author's Affiliation | / Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | |
| Date | 2006-06-09 |
| Paper # | ICD2006-57 |
| Volume (vol) | vol.106 |
| Number (no) | 92 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |