Presentation 2006-06-09
Design of a High-Performance Vision Processor with Shared-Memory Multi-SIMD Architecture
Kota YAMAGUCHI, Yoshihiro WATANABE, Takashi KOMURO, Masatoshi ISHIKAWA,
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Abstract(in English) For high speed image recognition in real environment, it is a challenge to accelerate a large amount of calculation for image processing from pre-processing to feature extraction. We designed a vision processor which consists of 2D/1D parallel SIMD and 0D sequential processor modules that share a memory. The processor has summation and broadcast function between modules, which accelerates complicated operations in image processing. Memory sharing reduces cost for data transferring between modules and simplifies implementation of various parallel algorithms. Simulation results show the processor can perform various image processings with much less operation steps.
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Keyword(in English) massively parallel processing / SIMD / image recognition LSI
Paper # ICD2006-56
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Conference Date 2006/6/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Design of a High-Performance Vision Processor with Shared-Memory Multi-SIMD Architecture
Sub Title (in English)
Keyword(1) massively parallel processing
Keyword(2) SIMD
Keyword(3) image recognition LSI
1st Author's Name Kota YAMAGUCHI
1st Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo()
2nd Author's Name Yoshihiro WATANABE
2nd Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo
3rd Author's Name Takashi KOMURO
3rd Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo
4th Author's Name Masatoshi ISHIKAWA
4th Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo
Date 2006-06-09
Paper # ICD2006-56
Volume (vol) vol.106
Number (no) 92
Page pp.pp.-
#Pages 6
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