Presentation 2006-06-09
A Superscalar Employing Instruction Decomposition for ARM Architecture
Yasuhiko NAKASHIMA,
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Abstract(in English) ARM architecture is one of de facto standard embedded processors and employs CISC-type instruction set that includes complex multiple load/store and so on. In general, it is difficult to execute CISC-type instructions in parallel with superscalar technique. This report shows the problems and the solutions for superscalar techniques that decompose ARM instructions into some RISC-type internal instructions. Finally, by evaluating the model with a pipeline simulator, the performance and the analysis are disclosed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ARM / Instruction Decomposition / Superscalar
Paper # ICD2006-54
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Committee ICD
Conference Date 2006/6/1(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Superscalar Employing Instruction Decomposition for ARM Architecture
Sub Title (in English)
Keyword(1) ARM
Keyword(2) Instruction Decomposition
Keyword(3) Superscalar
1st Author's Name Yasuhiko NAKASHIMA
1st Author's Affiliation Nara Institute of Science and Technology()
Date 2006-06-09
Paper # ICD2006-54
Volume (vol) vol.106
Number (no) 92
Page pp.pp.-
#Pages 6
Date of Issue