Presentation 2006-06-08
Design for Testability of Software-Based Self-Test for Processors
Masato NAKAZATO, Satoshi OHTAKE, Michiko INOUE, Hideo FUJIWARA,
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Abstract(in English) In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency in a sense that the proposed method completely resolves the problem of error masking. Moreover, the proposed method adds only observation points to the original design, it enables at-speed testing and does not induce delay overhead.
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Keyword(in English) software-based self-test / design for testability / processor / error mask / test program template
Paper # ICD2006-48
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Conference Date 2006/6/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design for Testability of Software-Based Self-Test for Processors
Sub Title (in English)
Keyword(1) software-based self-test
Keyword(2) design for testability
Keyword(3) processor
Keyword(4) error mask
Keyword(5) test program template
1st Author's Name Masato NAKAZATO
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology()
2nd Author's Name Satoshi OHTAKE
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
3rd Author's Name Michiko INOUE
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
4th Author's Name Hideo FUJIWARA
4th Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
Date 2006-06-08
Paper # ICD2006-48
Volume (vol) vol.106
Number (no) 92
Page pp.pp.-
#Pages 6
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