| Presentation | 2006-06-08 Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have investigated a technique for microprocessors, which achieves both high performance and low power. Based on the observation that critical paths in a circuit are not always active, we aggressively exploit timing violations in the circuit, which do not actually occur. We call the technique Constructive Timing Violation (CTV). Unfortunately, until now, we have evaluated the CTV without considering circuit delay. This paper presents evaluation results of a microprocessor utilizing the CTV, with considering circuit delay in adders. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Performance variations / Circuit delay / Simulations / Typical-case design methodologies |
| Paper # | ICD2006-47 |
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| Committee | ICD |
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| Conference Date | 2006/6/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation |
| Sub Title (in English) | |
| Keyword(1) | Performance variations |
| Keyword(2) | Circuit delay |
| Keyword(3) | Simulations |
| Keyword(4) | Typical-case design methodologies |
| 1st Author's Name | Yuji Kunitake |
| 1st Author's Affiliation | Department of Artificial Intelligence, Kyushu Institute of Technology() |
| 2nd Author's Name | Akihiro Chiyonobu |
| 2nd Author's Affiliation | Department of Artificial Intelligence, Kyushu Institute of Technology |
| 3rd Author's Name | Koichiro Tanaka |
| 3rd Author's Affiliation | Center for Microelectronic Systems, Kyushu Institute of Technology |
| 4th Author's Name | Toshinori Sato |
| 4th Author's Affiliation | System LSI Research Center, Kyushu University |
| Date | 2006-06-08 |
| Paper # | ICD2006-47 |
| Volume (vol) | vol.106 |
| Number (no) | 92 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |