Presentation 2006-06-08
Dynamic Voltage Scaling in an Elastic Pipeline and Its Application to an H.264/AVC HDTV Video Decoder LSI
Kentaro KAWAKAMI, Jun TAKEMURA, Mitsuhiko KURODA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO,
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Abstract(in English) We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The designed decoder reduces 48% of execution cycles for H.264 HDTV decoding. In case of DVS is applied with this reduced cycles, the proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.
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Keyword(in English) H.264/AVC / DVS (dynamic voltage scaling) / elastic pipeline / low power
Paper # ICD2006-45
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Conference Date 2006/6/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Dynamic Voltage Scaling in an Elastic Pipeline and Its Application to an H.264/AVC HDTV Video Decoder LSI
Sub Title (in English)
Keyword(1) H.264/AVC
Keyword(2) DVS (dynamic voltage scaling)
Keyword(3) elastic pipeline
Keyword(4) low power
1st Author's Name Kentaro KAWAKAMI
1st Author's Affiliation Graduate School of Science and Technology, Kobe University()
2nd Author's Name Jun TAKEMURA
2nd Author's Affiliation Graduate School of Natural Science & Technology, Kanazawa University
3rd Author's Name Mitsuhiko KURODA
3rd Author's Affiliation Computer and Systems Department, Kobe University
4th Author's Name Hiroshi KAWAGUCHI
4th Author's Affiliation Computer and Systems Department, Kobe University
5th Author's Name Masahiko YOSHIMOTO
5th Author's Affiliation Graduate School of Natural Science & Technology, Kanazawa University
Date 2006-06-08
Paper # ICD2006-45
Volume (vol) vol.106
Number (no) 92
Page pp.pp.-
#Pages 6
Date of Issue