Presentation 2006-06-08
Reducing Energy Consumption of the Dynamic Scheduling Logic by Instruction Grouping
Hiroshi SASAKI, Masaaki KONDO, Hiroshi NAKAMURA,
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Abstract(in English) Dynamic instruction scheduling logic is a quite complex component and dissipates significant energy in microprocessors which support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required number of ports and size of the structure. This paper describes the microarchitecture mechanisms and shows evaluation results on energy saving and performance.
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Keyword(in English) Dynamic Instruction Scheduling / Instruction Queue / Instruction Grouping
Paper # ICD2006-42
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Conference Date 2006/6/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reducing Energy Consumption of the Dynamic Scheduling Logic by Instruction Grouping
Sub Title (in English)
Keyword(1) Dynamic Instruction Scheduling
Keyword(2) Instruction Queue
Keyword(3) Instruction Grouping
1st Author's Name Hiroshi SASAKI
1st Author's Affiliation Research Center for Advanced Science and Technology The University of Tokyo()
2nd Author's Name Masaaki KONDO
2nd Author's Affiliation Research Center for Advanced Science and Technology The University of Tokyo
3rd Author's Name Hiroshi NAKAMURA
3rd Author's Affiliation Research Center for Advanced Science and Technology The University of Tokyo
Date 2006-06-08
Paper # ICD2006-42
Volume (vol) vol.106
Number (no) 92
Page pp.pp.-
#Pages 6
Date of Issue