Presentation 2006-05-19
FPGA-based Processor for Computational Fluid Dynamics
Takanori IIZUKA, Kentaro SANO, Satoru YAMAMOTO,
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Abstract(in English) This paper presents an FPGA-based flow solver based on the systolic architecture. We show that a flow solver based on the fractional-step method with difference schemes can be expressed as a systolic algorithm, and the systolic architecture is suitable to design the special-purpose processor for the flow solver. Based on this architecture, we propose the special-purpose processor comprised of a 2D array of cells connected by a 2D mesh network. Each cell has a computational data-path and a local memory. While the whole array stores data as a memory, it also performs highly parallel and scalable floating-point computations with the sufficient memory bandwidth. We report the initial design of the processor for two ALTERA Stratix II FPGAs, and discuss its estimated performance that the peak performance of 30 Gflops could be achieved at only 60MHz.
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Keyword(in English) FPGA / CFD / systoric array / special-purpose processor
Paper # RECONF2006-13
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Conference Information
Committee RECONF
Conference Date 2006/5/12(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) FPGA-based Processor for Computational Fluid Dynamics
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) CFD
Keyword(3) systoric array
Keyword(4) special-purpose processor
1st Author's Name Takanori IIZUKA
1st Author's Affiliation Graduated School of Information Science, Tohoku University()
2nd Author's Name Kentaro SANO
2nd Author's Affiliation Graduated School of Information Science, Tohoku University
3rd Author's Name Satoru YAMAMOTO
3rd Author's Affiliation Graduated School of Information Science, Tohoku University
Date 2006-05-19
Paper # RECONF2006-13
Volume (vol) vol.106
Number (no) 50
Page pp.pp.-
#Pages 6
Date of Issue