Presentation 2006-05-18
Reconfigurable Architectures with On-Chip Networks for Multitask Designs
Yohei HASEGAWA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO,
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Abstract(in English) A reconfigurable processor architecture which employs on-chip networks to connect multiple reconfigurable cores. Both the processed stream data and configuration data are integrated into a single packet and transferred in a unique network. Two application execution methods: task-level pipelining policy and configuration moving policy can be applied into the proposed architecture. Since these methods require different communication traffic, analysis of the network performance is indispensable. In this report, we designed each task of the JPEG encoder on the NEC electronics' DRP-1, and evaluated the performance of two execution methods using the flit-level network simulator. As a result, the pipelining policy outperformed the configuration moving policy from the viewpoint of the throughput. Even in the case of configuration moving policy, simulation result shows that the configuration cache can distribute the configuration data between each core to improve the throughput.
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Keyword(in English) Reconfigurable Architectures / On-Chip Networks / Multitasking / Stream Processing
Paper # RECONF2006-5
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Conference Information
Committee RECONF
Conference Date 2006/5/11(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reconfigurable Architectures with On-Chip Networks for Multitask Designs
Sub Title (in English)
Keyword(1) Reconfigurable Architectures
Keyword(2) On-Chip Networks
Keyword(3) Multitasking
Keyword(4) Stream Processing
1st Author's Name Yohei HASEGAWA
1st Author's Affiliation Department of Information and Computer Science, Keio University()
2nd Author's Name Hiroki MATSUTANI
2nd Author's Affiliation Department of Information and Computer Science, Keio University
3rd Author's Name Michihiro KOIBUCHI
3rd Author's Affiliation National Institute of Informatics
4th Author's Name Hideharu AMANO
4th Author's Affiliation Department of Information and Computer Science, Keio University
Date 2006-05-18
Paper # RECONF2006-5
Volume (vol) vol.106
Number (no) 49
Page pp.pp.-
#Pages 6
Date of Issue