| Presentation | 2006-05-18 A Study of Mapping Method for Variable Grain Logic Cell Architecture Ryoichi YAMAGUCHI, Kazunori MATUYAMA, Hideaki NAKAYAMA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Reconfigurable logic devices are usually classified on the basis of their basic logic cell architecture as fine-grain or coarse-grain. The coarse-grained architecture is suitable for the byte processing. On the other hand, the fine-grained architecture is suitable for the bit processing. Because there are suitable operations for each devices, it is a problem that applications are limited by a kind of device. To solve this problem, we propose variable grain logic cell that can be implemented full adder and the same function of LUT. Our proposed logic cell has various functional modes. Therefore, when we map logical operations, our logic cell is larger than conventional LUTs in the number of transistors and configuration memory bits. In this paper, we show a mapping method utilizing the gate structure in order to reduce the cost of logical operations. As a result, the mapping method achieves the same number of transistors and reduces configuration memory bits by 43% in comparison with conventional 4-LUT. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic device / coarse-grain / fine-grain |
| Paper # | RECONF2006-1 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Mapping Method for Variable Grain Logic Cell Architecture |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic device |
| Keyword(2) | coarse-grain |
| Keyword(3) | fine-grain |
| 1st Author's Name | Ryoichi YAMAGUCHI |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Kazunori MATUYAMA |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Hideaki NAKAYAMA |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Motoki AMAGASAKI |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Masahiro IIDA |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 6th Author's Name | Toshinori SUEYOSHI |
| 6th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2006-05-18 |
| Paper # | RECONF2006-1 |
| Volume (vol) | vol.106 |
| Number (no) | 49 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |