| Presentation | 2006-05-19 Bit-Transition Differential Power Analysis on FPGA Implementaion of Block Cipher with Masking Countermeasure Yoshio TAKAHASHI, Tsutomu MATSUMOTO, Akashi SATOH, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The Akkar and Giraud's masking countermeasure (AG-Masking Countermeasure) that masks the intermediate data with random number make Differential Power Analysis (DPA) in feasible or increases the cost of DPA. To disturb the conventional DPA using the correlation between power traces and bit value of the intermediate data, this countermesure aims to destroy the correlation by concealing the bit value with random masking. However, even if DPA on bit-value is impossible, bit-transition DPA has the possibility of succeeding in the attack of the AG-Masking Countermeasure in the same cost. In this paper, we analyzed the feasibility of bit transion DPA against FPGA implementaion of DES cipher with AG-Masking Countermeasure. We implemented an AG-Masked-DES on FPGA board and experimented on the DPA attacks. The experimental results show that all bit of key were correctly obtained from AG-Masked-DES with the same number of power traces to break a unmasked-DES. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Side Channel Attacks / Differential Power Analysis / bit-transition DPA / Masking method / Block cipher / DES / FPGA |
| Paper # | ISEC2006-1 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2006/5/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Bit-Transition Differential Power Analysis on FPGA Implementaion of Block Cipher with Masking Countermeasure |
| Sub Title (in English) | |
| Keyword(1) | Side Channel Attacks |
| Keyword(2) | Differential Power Analysis |
| Keyword(3) | bit-transition DPA |
| Keyword(4) | Masking method |
| Keyword(5) | Block cipher |
| Keyword(6) | DES |
| Keyword(7) | FPGA |
| 1st Author's Name | Yoshio TAKAHASHI |
| 1st Author's Affiliation | NTT DATA Corporation, R&D Headquaters, Kayabacho Tower Bldg.:Graduate School of Environment and Information Sciences, Yokohama National University() |
| 2nd Author's Name | Tsutomu MATSUMOTO |
| 2nd Author's Affiliation | Graduate School of Environment and Information Sciences, Yokohama National University |
| 3rd Author's Name | Akashi SATOH |
| 3rd Author's Affiliation | IBM Japan, Ltd., IBM Research, Tokyo Research Laboratory |
| Date | 2006-05-19 |
| Paper # | ISEC2006-1 |
| Volume (vol) | vol.106 |
| Number (no) | 51 |
| Page | pp.pp.- |
| #Pages | 6 |
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